The present invention relates to semiconductor structures and methods for fabricating such structures in semiconductor integrated circuits, and in particular, to forming capacitors for memory cells having high dielectric constant materials therein.
Dynamic random access memories (DRAMs) are the most widely used form of semiconductor memory to date. DRAMs are composed of memory cell arrays and peripheral circuitry required for cell access and external input and output. Each memory cell array is formed of a plurality of memory cells for storing bits of data. Typical memory cells are formed of a capacitor, for storing electric charges and a transistor, for controlling charge and discharge of the capacitor. Of primary concern is maximizing the storage capacitance of each memory cell capacitor, particularly in light of the demand for 256 Mb DRAMs today and higher densities in the future without increasing the chip space required to form the array. There is a need to decrease the chip space required to form each memory cell while maximizing the capacitance of the memory cells. The importance of high density DRAMs can not be overstated in today""s competitive micro electronics market. Devices are becoming smaller, but they are required to provide much more performance.
One way to achieve greater capacitance per unit area is to roughen the surface of the capacitor plate, increasing the surface area. As can be seen from the following equation (I), the most important parameters involved in achieving maximum charge, Q, stored on the capacitor are the thickness of the capacitive dielectric film (tcdf), the area of the capacitor (A), and the dielectric constant (xcex5). The voltage applied to the gate is Vg.
xe2x80x83Q=(xcex5xc2x7Axc2x7Vg)/tcdfxe2x80x83xe2x80x83(I)
Increasing the capacitor area (A) by forming the storage capacitor in a trench shape etched in the substrate is well known in the art, as well as using a stacked capacitor structure. Stacked-type capacitors feature a major part of the capacitor extending over the gate electrode and field isolating film of the underlying transistor. Such structures are generally composed of a lower plate electrode (consisting of a base portion a standing wall portion), a capacitive dielectric film, and an upper plate electrode. Other complex topographical lower plate electrode configurations have also been used to maximize the capacitive area (A) of a memory cell, such as fin-type, double-sided, and roughened lower plate electrode structures produced using hemispherical grain (HSG) polysilicon.
In addition to increasing the capacitive surface area (A) of a memory cell, as can be seen from the above equation (I), the thickness of the capacitive dielectric film (tcdf) must be as thin as possible to maintain the maximum charge stored on the capacitor. However, the capacitive dielectric film must also prevent direct electrical contact between the lower and upper electrodes.
It is also desirable to utilize a capacitive dielectric film having as high of a dielectric constant (xcex5) as possible to further increase the capacitance per unit area of a memory cell. Known high dielectric constant (HDC) materials include: tantalum penta oxide (ta2O5), yttria (Y2O3), titanium oxide (TiO2), strontium bismuth titanate (SBT), lead zirconate titanate (PZT), lanthanum-doped lead zirconate titanate (PLZT), barium strontium titanate (BST), bismuth titanate (BTO), strontium titanate (STO), barium titanate (BTO), and polymeric materials. A dielectric constant (xcex5) of greater than 7 is typically considered to be a HDC material. For example, Ta2O5 potentially has a dielectric constant (xcex5) more than 20 times greater than conventional silicon oxide, which has a dielectric constant (xcex5) of 3.9. BST has a dielectric constant (xcex5) about 100 times as large as that of a conventional silicon oxide film or a silicon nitride (xcex5about 7) film.
Currently, the use of HDC materials within a capacitor memory cell is limited by the instability of HDC materials and other component materials in an integrated circuit at higher temperatures. Such higher temperatures are required to treat the surface of HDC materials to conform to adjacent electrodes during the fabrication process. Furthermore, many of these HDC materials are ceramic in nature when formed in a thin layer, being so characterized by having low density. It is undesirable to utilize such low density materials in an application requiring a very thin layer of the material, because it allows current leakage through the capacitive dielectric film, degrading device performance. Thus, high temperature steps are often needed to densify/condition HDC materials.
It is undesirable to utilize high temperature steps during the fabrication of integrated circuits because high temperature steps consume valuable thermal budget. The thermal budget for an integrated circuit is that combination of maximum time and temperature for heat treatments utilized in the fabrication of the integrated circuit. An integrated circuit can only be subjected to a limited number of thermal steps for a limited amount of time before its electrical performance is potentially detrimentally affected. For example, thermal steps often cause dopant gradients at junctions between two regions in an integrated circuit to diffuse, such that the potential barrier between the two regions is altered. Furthermore, thermal steps often cause dopants to migrate into undesired regions, altering device characteristics. Since access transistors are formed prior to the capacitor in many DRAM devices, it is not desirable to use high temperatures to form the capacitor.
Due to the limitations of such HDC materials and methods for their formation, silicon oxide and silicon nitride are commonly used in capacitive memory cells. In order to minimize the thickness of the cell capacitive dielectric film and further increase the cell capacitance, silicon nitride is commonly used in such memory cells due to its superior qualities as compared to silicon oxide (another commonly used dielectric in semiconductor integrated circuit fabrication) at such thicknesses. At thicknesses of 100 angstroms or less, silicon oxide exhibits a high defect density. Silicon oxide is further undesirable for use in memory cells due to its comparatively low dielectric constant (xcex5).
While silicon nitride is superior to silicon oxide at thicknesses below 100 angstroms, silicon nitride also has problems of its own. Pinholes, extending throughout a silicon nitride layer, often present in such silicon nitride films, lead to current leakage, which decreases capacitance and can further degrade devices over time, making them unreliable. However, the leakage current seen in silicon nitride films is typically not of the same magnitude as that seen in HDC films previously described. One attempt in overcoming the pinhole problem in silicon nitride films is to form a plurality of silicon nitride layers in place of a single layer, chancing the occurrence that pinholes in adjacent layers will not be aligned, thus preventing current leakage. However, this technique is not reliable and its use is limited in today""s devices due to the need to make devices as small as possible.
There is a need for a method of forming capacitor memory cells having increased capacitance per unit area. Thus, there is a need for utilizing a HDC material as the capacitive dielectric film in a capacitor cell, in order to increase the capacitance per unit area in a memory cell. A method for integrating such HDC materials within a capacitor memory cell, such that the HDC material is relatively stable and has a relatively low leakage current, and a method utilizing a minimal amount of the thermal budget is needed. It is further desirable to form a capacitive dielectric film that is as thin and dense as possible, in order to conserve device density, decrease leakage current, and increase the capacitance per unit area in the memory cell.
The present invention teaches a method and apparatus for forming a capacitive memory cell, such as a dynamic random access memory (DRAM) cell, utilizing a high dielectric constant (HDC) material for the capacitive dielectric film. A bottom plate electrode of known shapes and topographies is prepared according to well known techniques. Then, the bottom plate electrode is cleaned as well known to one skilled in the art.
In one embodiment, a polysilicon, crystalline silicon, hemispherical grain polysilicon, germanium, or silicon-germanium bottom plate electrode material is used and the bottom plate electrode is subjected to a relatively high pressure surface treatment after its formation. The relatively high pressure surface treatment comprises one of rapid thermal nitridation (RTN) or oxidation (in an O2, NO, or N2O ambient). When HDC materials, such as tantalum penta oxide (Ta2O5), yttria (Y2O3), or titanium oxide (TiO2), all having a dielectric constant of approximately less than 100, are used for a capacitive dielectric film, RTN is typically used. A nitrogen-containing reactant gas, such as ammonia or hydrazine, is used during a RTN step.
When a batch-type processing chamber is used, a processing chamber pressure of up to approximately 100 atmospheres is used for the relatively high pressure surface treatment. Typically, processing chamber pressures of approximately 1 to 25 atmospheres suffice to effectuate the invention in a batch-type processing chamber. When a single wafer processing chamber is used, a processing chamber pressure of at least 1 atmosphere or higher is used for the high pressure surface treatment. Typically, processing chamber pressures of approximately 25 to 600 atmospheres suffice to effectuate the invention in a single wafer processing chamber.
By utilizing relatively high pressure for the surface treatment, surface treatment temperatures are reduced to approximately 100 degrees Celsius or higher, conserving valuable thermal budget during the integrated circuit fabrication process. Typically, processing chamber temperatures of approximately 200 to 950 degrees Celsius are used when practicing the invention. Cold wall or hot wall type processing chambers can be used to practice the invention. Heating methods are well known to those skilled in the art, including resistive heating and rapid thermal processing.
Next, a HDC material (i.e., a material having a dielectric constant (xcex5) of 7 or greater) is formed as a capacitive dielectric film on the bottom plate electrode. The method for forming HDC materials is well known to one skilled in the art. Such HDC materials include: tantalum penta oxide (Ta2O5), yttria (Y2O3), titanium oxide (TiO2), strontium bismuth titanate (SBT), lead zirconate titanate (PZT), lanthanum-doped lead zirconate titanate (PLZT), barium strontium titanate (BST), bismuth titanate (BiTO), strontium titanate (STO), barium titanate (BaTO), and polymeric materials. Inorganic or organic precursors, both liquids and/or solids, are used for starting materials when depositing such HDC materials. HDC materials are deposited in any manner known to those skilled in the art, including physical vapor deposition, chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and rapid thermal chemical vapor deposition (RTCVD).
The capacitive dielectric film is then subjected to a relatively high pressure surface treatment to densify/condition the material. The relatively high pressure surface treatment comprises oxidation (in an O2, NO, or N2O ambient). Oxidation tends to fill oxygen vacancies often present in the lattice structure of as-deposited HDC materials, densifying/conditioning the capacitive dielectric film and increasing its capacitance.
As in the bottom plate electrode relatively high pressure surface treatment, when a batch-type processing chamber is used, a processing chamber pressure of up to approximately 100 atmospheres is used for the relatively high pressure surface treatment. Typically, processing chamber pressures of approximately 1 to 25 atmospheres suffice to effectuate the invention in a batch-type processing chamber. When a single wafer processing chamber is used, a processing chamber pressure of at least 1 atmosphere or higher is used for the high pressure surface treatment. Typically, processing chamber pressures of approximately 25 to 600 atmospheres suffice to effectuate the invention in a single wafer processing chamber.
By utilizing relatively high pressure for the surface treatment, surface treatment temperatures are reduced to approximately 100 degrees Celsius or higher, conserving valuable thermal budget during the integrated circuit fabrication process. Typically, processing chamber temperatures of approximately 200 to 950 degrees Celsius are used when practicing the invention.
In another embodiment of the invention, a metallic material, such as titanium, titanium nitride, platinum, platinum-aluminum, rhodium, rhodium oxide, cesium oxide, or strontium rhodium oxide (SRO), is used for the bottom plate electrode. When a metallic material is used for the bottom plate electrode, a relatively high pressure surface treatment is not needed prior to forming the capacitive dielectric film thereon because the diffusion problem of silicon/HDC material interfaces is not present.
Next, a HDC material (i.e., a material having a dielectric constant (xcex5) of 7 or greater) is formed as a capacitive dielectric film on the metallic bottom plate electrode. The method for forming HDC materials is well known to one skilled in the art. Such HDC materials include: tantalum penta oxide (Ta2O5), yttria (Y2O3), titanium oxide (TiO2), strontium bismuth titanate (SBT), lead zirconate titanate (PZT), lanthanum-doped lead zirconate titanate (PLZT), barium strontium titanate (BST), bismuth titanate (BiTO), strontium titanate (STO), barium titanate (BaTO), and polymeric materials.
The capacitive dielectric film is then subjected to a relatively high pressure surface treatment to densify/condition the material. The relatively high pressure surface treatment comprises oxidation (in an O2, NO, or N2O ambient). Oxidation tends to fill oxygen vacancies often present in the lattice structure of as-deposited HDC materials, densifying/conditioning the capacitive dielectric film and increasing its capacitance.
When a batch-type processing chamber is used, a processing chamber pressure of up to approximately 100 atmospheres is used for the relatively high pressure surface treatment. Typically, processing chamber pressures of approximately 1 to 25 atmospheres suffice to effectuate the invention in a batch-type processing chamber. When a single wafer processing chamber is used, a processing chamber pressure of at least 1 atmosphere or higher is used for the high pressure surface treatment. Typically, processing chamber pressures of approximately 25 to 600 atmospheres suffice to effectuate the invention in a single wafer processing chamber.
By utilizing relatively high pressure for the surface treatment, surface treatment temperatures are reduced to approximately 100 degrees Celsius or higher, conserving valuable thermal budget during the integrated circuit fabrication process. Typically, processing chamber temperatures of approximately 200 to 950 degrees Celsius are used when practicing the invention. Cold wall or hot wall type processing chambers can be used to practice the invention. Heating methods are well known to those skilled in the art, including resistive heating and rapid thermal processing.
To complete formation of the capacitor structure in both embodiments described previously, a top plate electrode is formed on the capacitive dielectric film as well known to one skilled in the art. The resulting capacitor has an increased capacitance per unit area as compared to previously used capacitors, due to its effective incorporation of a HDC material. Thus, the capacitor structure of the present invention is advantageously used in memories, such as DRAMs, enabling memories to be made more dense, as demanded by current consumers.
Surface treatments are typically needed to densify/condition the dielectric material and provide a barrier layer between the electrode and the dielectric materials. By utilizing the method of the invention, a HDC material is able to be deposited effectively on a bottom plate electrode. Previously, HDC materials, such as Ta2O5, were unable to be used adjacent to a polysilicon surface because of the tendency for the two materials to react in an uncontrolled manner, forming silicon oxide at the polysilicon/Ta2O5 interface. It is advantageous to use polysilicon for the bottom plate electrode because the same layer of polysilicon can be used as is used in other parts of an integrated circuit, such as for the gate of an access transistor. While a thin diffusion barrier layer (Si3N4 or SiO2) is needed between the polysilicon bottom plate electrode and the HDC capacitive dielectric film, it is undesirable for the diffusion barrier layer to become too thick. This undesirable consequence is prevented by using relatively high pressure surface treatments of the present invention.